1. Field of the Invention
The present invention relates to data generating apparatus, and more particularly, to a data generating apparatus for sequentially generating consecutive data, and a method of operating the same.
2. Description of the Background Art
Large memory capacity is required for memories of computers and image processing devices in accordance with the development of recent techniques. Random access memories (RAM) are used for the memories of such computers, and sequential memories are used for image processing devices.
A RAM is supplied with an arbitrary address signal, whereby access is carried out with respect to the arbitrary address. A sequential memory is supplied with address signals incremented by "1", whereby sequential access is carried out with respect to consecutive addresses.
FIG. 13 is a schematic block diagram of a one-chip sequential memory device. Referring to FIG. 13, the sequential memory device comprises a timing generating circuit 90, a binary counter 100, and a sequential memory 6. Timing generating circuit 90 responds to an externally applied clock signal CLK1 to generate a clock signal CLK2 for controlling the address data output timing of binary counter 100, and a read/write specifying signal R/W for specifying the reading or the writing of sequential memory 6. Binary counter 100 responds to clock signal CLK2 to sequentially increment an address data by "1". In response to read/write specifying signal R/W and the updated address data, an externally applied data is written into sequential memory 6 sequentially. Later on, data stored in sequential memory 6 is read out to an external source sequentially.
FIG. 14 is a block diagram of a conventional binary counter of 3-bit structure described in "PRINCIPLES OF CMOS VLSI DESIGN" by Neil H. E. Weste, Kamran Eshraghian, ADDISON-WESLEY PUBLISHING COMPANY, p. 338. Referring to FIG. 14, the binary counter comprises adders 11, 12, and 13, and D type flipflop circuits (hereinafter referred to as D-FF) 21, 22, and 23. The outputs of D-FFs 21, 22 and 23 are provided to the address terminal of the sequential memory.
FIG. 15 is the circuit diagram of the aforementioned adder. Referring to FIG. 15, the adder comprises input terminals A and B, a carry input terminal Ci, a sum output terminal S for providing the summed result, a carry output terminal Co, inverters 1a, 1b, 1e, 1f, and 1g and in, and complementary MOSFETs 1c, 1d, 1h, 1j and 1k. The above mentioned adder carries out adding processing. That is to say, when the signals at input terminals A and B are both "1", the output Co becomes "1" regardless of carry input Ci. When the signals at input terminals A and B are both "0", carry output Co is "0" regardless of carry input Ci. When either the signal at input terminal A or B is "0", the preceding logic state is maintained.
The operation of the binary counter 100 of FIGS. 14 and 15 will be explained hereinafter.
The potential of input terminal B of adder 11 among the adders 11, 12, 13 is always at the high level, while the potentials of input terminal B of adders 12 and 13 are always at the low level. Adder 11 therefore adds "1" to the preceding state every time an output signal is applied to input terminal A from D-FF21. Every time the added result is "0", a carry flag is provided from carry output terminal Co to adder 12 of the more significant bit. Adder 12 provides a carry flag to adder 13 of the more significant bit every time the summed result is "0". The aforementioned plurality of adders are called ripple adders because carry bits are operated in a chained manner.
D-FFs 21, 22, and 23 are responsive to the input of the clock signal CLK2 to provide the summed result to the sequential memory, as well as to input terminals A of adders 11, 12 and 13.
Thus, the address of the sequential memory can be specified with a serial number by using a binary counter incrementing "1" to the preceding logic state.
A binary counter can be used in the RAM of a computer if the address is counted sequentially (for example, program counter).
If there is a faulty bit in the address of the sequential memory, the address with the faulty bit will be specified because "1" is incremented to the preceding logic state in the binary counter of the aforementioned structure. If there is an error bit in a region of the sequential memory, it is necessary to exchange the entire sequential memory, even if there are no faulty bits in other regions.